This invention relates to integrated circuits incorporating a boundary scan architecture for enabling interconnect and corelogic function testing.
Integrated circuits are increasingly being designed with a boundary scan test capability in order to facilitate the testing of manufactured integrated circuits for proper pin connections and corelogic functionality. In a boundary scan integrated circuit, the corelogic is surrounded by a multiplicity of individual boundary scan cells each coupled between a different device terminal and the corelogic element coupled to that device terminal. The boundary scan cells are all serially connected, and the first and last boundary cells in the chain are coupled, respectively, to the test data input and the test data output of a boundary scan test access port. When the integrated circuit is powered up for normal use, the individual boundary scan cells are transparent. However, when a boundary scan test is being performed, individual ones of the boundary scan cells are activated by means of instructions supplied from an external controller usually termed an initiator. Each instruction is loaded into a boundary scan instruction register and is decoded by a boundary scan decoder element and used to test the integrity of the terminal-to-corelogic individual connections and also the functionality of at least some of the corelogic elements. This boundary scan test is usually performed as part of the manufacturing operation, but is increasingly being used as part of a field service capability. The resultant test data is sent back to the initiator for evaluation. Communication between the boundary scan initiator and the boundary scan test circuits are over a small bus (usually four bits wide) termed a boundary scan bus.
The test access port of the boundary scan architecture typically includes a test data input, a test data output, a test clock input and a test mode select input. Input test data, such as boundary scan test instructions, are serially clocked into the boundary scan instruction register by means of the test clock signal and the mode of operation of the boundary scan circuitry is controlled by the test mode select control signal.
When testing a plurality of boundary scan integrated circuits mounted on a single printed circuit board, the boundary scan registers for the individual integrated circuits are either connected in series to form a single boundary scan path through the connection of integrated circuits, or are connected in a parallel arrangement to contain several independent boundary scan paths.
In order to ensure that the boundary scan path itself is functional, the boundary scan circuitry on each integrated circuit is provided with logic circuitry for loading into the boundary scan instruction register a predetermined sentinel bit pattern downstream of an incoming instruction. As the instruction is serially shifted into the instruction register, the sentinel bit pattern is shifted out to the test data output terminal of the test access port, and is coupled to the boundary scan initiator. If the sentinel bit pattern is correct, this verifies the integrity of the boundary scan paths. If not, a discontinuity somewhere along the boundary scan path is indicated. In the case of several integrated circuits each incorporating boundary scan architecture and linked to the boundary scan bus in series, the sentinel bits corresponding to each integrated circuit are checked by the boundary scan initiator to test for boundary scan bus continuity.
In known devices, this sentinel protocol is incapable of indicating whether the boundary scan bus discontinuity exists upstream of the instruction register or downstream of the instruction register. This inability to isolate the location of the fault complicates the task of repairing a fault in the boundary scan bus.